Advances in semiconductor design methods and fabrication technologies are leading to a continuous increase in the complexity of Integrated Circuits (ICs). A modern IC not only includes a plurality of transistors, but also operates at a higher clock frequency. These advances such as higher clock frequencies make the modern IC more susceptible to timing related defects, such as Small Delay Defects (SDDs). While an IC designer may design an IC in accordance with its timing specification, due to process variations and manufacture defects, some ICs may still fail the SDD test. Therefore, testing for SDDs is an important step to separate defective chips from non-defective chips.
SDDs involve small delay variations in ICs due to semiconductor fabrication process variations, power supply noise, crosstalk noise and the like. A traditional Transition Delay Fault (TDF) method may not detect SDDS because the delay captured by the TDF method at each logic gate is small and within specifications. However, the cumulative delay at a critical path having a plurality of logic gates in series connection may cause a logic failure. In order to detect a SDD failure in an IC, a least slack time path in the IC is selected to activate the SDD induced fault. The least slack time path may be a long path having a variety of logic gates and wires.
A variety of Automatic Test Pattern Generation (ATPG) methods have been applied to detecting SDDs. Faster-than-at-speed delay tests perform a reliable SDD test at a short path by removing as much of the slack as possible. In other words, the slack at a short path can be removed by increasing the clocking speed of test patterns. Although this method can activate SDDs by removing the slack time in ICs, the higher frequency of this method requires additional design and test constraints, which may be complicated. In addition, this method may reject some good ICs having additional delays which may not cause logic failures in real applications. Furthermore, the higher frequency of this method may increase power consumption to a level exceeding the maximum value to which the IC is specified.
A timing-aware ATPG method is another approach to effectively detect SDDs. Instead of removing the slack time at a short path, the timing-aware ATPG method excites SDDs through long paths. Such a timing-aware method uses timing information of an IC and selects a list of long paths having least slack time, so that the timing-aware ATPG method may have a high possibility of finding SDDs. However, the number of pattern count and run time may increase exponentially as feature sizes of ICs increase. This may slow down the real performance of the timing-aware ATPG method.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.